The present invention relates to the design and fabrication of microelectronic elements, e.g., integrated circuits including microelectronic devices.
Various approaches have been used to optimize the performance of transistors of a layout during the circuit design phase of design. For example in commonly assigned co-pending U.S. application Ser. No. 11/278,162 to Christopher J. Gonzalez et al. entitled “Method for Implementing Overlay-Based Modification of VLSI Design Layout”, the performance of individual transistors can be maximized by moving the boundaries of n-wells (doped semiconductor regions) of the transistors outwards as far from the channels of the transistors as allowed by design rules. This approach would be advantageous when most devices in the layout are weaker than the reference device of the compact model, the compact model representing the device layout with a reference performance level. Then, it is possible to apply a process which only improves the performance of all the devices, since moving the boundaries in one direction only is straightforward, and the boundaries can be moved to positions where the device can readily conform to the reference device of the compact model. However, sometimes it is intended per design intent that some devices of a layout are required to be either weaker or stronger than the reference device of the compact model. Then, while it is desirable to change the performance of that device (while preserving the performance of the surrounding devices in the circuit design) the specific direction of moving the edge has to be modified through a set of instructions relative to design intent.
In another example, as described in commonly owned United States Patent Publication No. 2007/0028195 to Dureseti Chidambarrao et al. entitled “Methodology For Layout-Based Modulation And Optimization Of Nitride Liner Stress Effect In Compact Models,” the effect of a change in a stressed liner of a transistor on the performance of that transistor can be modeled.